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W631GG6KB
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
Command
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
Address
ODTH4
ODT
RTT
DQS, DQS#
DQ
ODTLon
t AONmin
t AONmax
Rtt_Nom
ODTLoff
t AOFmin
t AOFmax
TRANSITIONING
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 78 – Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
DON'T CARE
CK#
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK
ODTLcnw
Command
NOP
WRS8
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
VALID
ODTH8
ODT
RTT
ODTLon
t AONmin
Rtt_WR
ODTLoff
t AOFmin
DQS, DQS#
ODTLcwn8
t ADCmax
t AOFmax
DQ
WL
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
TRANSITIONING
DON'T CARE
Note:
1. Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
Figure 79 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles
Publication Release Date: Dec. 09, 2013
Revision A05
- 86 -
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